module tb_controlUnit_init();
    reg G, clk, reset, Q, Z;
    wire on;
    wire [2:0] Csignal;
    controlUnit dut(Q, Z, G, reset, clk, Csignal);
    always
    begin
        clk=1; #5; clk=0; #5;
    end

    initial begin
        $dumpfile("tb_controlUnit");
        $dumpvars;
        G = 0;reset=1;Q=0;Z=0;#10;
        G=1; reset = 0;#20;
        G=0;#10;
        G=1;#10;
        Q=1;#15;
        Q=0;#5;
        Z=1;#5;
        Z=0;#10;
        Z=1;Q=1;#30;
        Z=0;Q=0;#25;
        G=0;#30;
        $finish;
    end
endmodule

